Many phases of modern electronic design are performed with computer aided design (CAD) tools or electronic design automation (EDA) systems. To design an integrated circuit, a designer first creates high level behavior descriptions of the IC device using a high-level hardware design language (HDL). Common examples of HDLs include Verilog and VHDL. An EDA system typically receives the high level behavior descriptions of the IC device and translates this high-level design language into netlists of various levels of abstraction using a computer synthesis process. A netlist describes interconnections of nodes and components on the chip and includes information of circuit primitives such as transistors and diodes, their sizes and interconnections, for example.
Verification is a necessary step in the design cycle to ensure that the electronic circuit design will work for its intended purpose. After a circuit designer has created an initial design, the designer will typically perform verification and analysis upon the integrated circuit using a set of EDA verification tools.
As the quantity of data in modern electronic designs become larger and larger over time, it has become apparent that conventional EDA verification tools are unable to effectively and efficiently scale upwards to handle very large electronic designs, such as many modern microprocessor, SOC, and systems designs. For example, the ability of conventional verification tools to handle simulation or formal verification is incompatible with many modern integrated circuit (IC) designs being produced by electronics companies that are constantly increasing in complexity and number of transistors. The basic problem is that conventional simulation and formal verification tools are designed to handle much smaller sets of data than exists for modern designs. Due to the extremely large volume of data (e.g., RTL or register transfer level data) for many modern electronic designs, it is a very expensive and time-consuming process to verify large modern designs using conventional verification tools. With the modern trend towards increased functionality and feature sets for modern IC chips, as well as constantly improving IC manufacturing technologies that can create IC chips at ever-smaller feature sizes, this means that there are increasingly greater quantities of transistors and other objects to be placed within the same chip area that must be verified. This further renders conventional verification tools impractical for the job of verifying modern designs.
One possible approach that can be taken to address this problem is to perform verification of a circuit design at a higher level of abstraction. For example, transaction based verification is one possible approach for performing verification at a more abstracted level. With transaction based verification, low level signal activities are grouped together into common “transactions” and abstracted out, effectively removed from the model, and replace by function calls into a transaction level model (TLM). The idea is that verification at a higher abstraction level will provide faster and less expensive verification results due to the smaller amount of signal transitions that need to be simulated and data that must be verified.
The problem with this approach is that conventional transaction based verification tools do not provide a guarantee of relationship between the different abstraction levels. Therefore, there is no guarantee that error-free results identified at the transaction level will translate into error-free results at the signal level, and vice versa. As a result, an electronic design that undergoes TLM-based based verification will nonetheless also need to undergo complete RTL-based verification processing to ensure that there are no errors in the design (along with the costly time requirements and computing costs that go along with verification of full RTL for a circuit). As such, one may wonder why the transaction based verification even needs to be performed under this circumstance.
Therefore, there is a need for an improved approach to verification that can adequately handle large modern electronic designs.